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ESPRESSIF

ESPRESSIF ESP32-S2 2.4 GHz Wi-Fi MCU 2.4 GHz Wi-Fi 240 MHz LX7 43 GPIOs

SoCs · ESPRESSIF

MPNESP32-S2

USB device/host ready: Full-speed USB OTG with on-chip PHY streamlines accessories and field update paths. ULP always-on sensing: A dedicated ULP coprocessor handles RTC GPIO/ADC/touch while the main CPU sleeps. Hardened security chain: Secure boot + flash encryption + hardware AES/SHA/RSA and true RNG.

CPU
Xtensa® single-core 32-bit LX7, up to 240 MHz; 7-stage pipeline, 32 interrupts (6 levels)
Wi-Fi
IEEE 802.11b/g/n (2.4 GHz), 20/40 MHz channels, 1T1R, up to 150 Mb/s; antenna diversity; 802.11mc FTM
MAC modes
Simultaneous Station / SoftAP / Promiscuous; 4 virtual interfaces; WMM; A-MPDU/A-MSDU; Immediate Block ACK
On-chip memory
320 KB SRAM + 128 KB ROM; RTC FAST/SLOW 8 KB each; 4 Kbit eFuse (≈1792 bits user)
External memory
SPI/QSPI/OSPI/OPI flash & RAM, up to 1 GB addressable; cache-accelerated XIP; flash ICP support
Integrated options
Variants with embedded Flash (2 MB, 4 MB) and/or embedded PSRAM (2 MB): ESP32-S2FH2/FH4/FN4R2/R2
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Specifications

Reference table for ESP32-S2: 12 electrical and mechanical values from ESPRESSIF data, ready to copy into your design notes.

ParameterValueParameterValue
CPUXtensa® single-core 32-bit LX7, up to 240 MHz; 7-stage pipeline, 32 interrupts (6 levels)GPIO43 programmable GPIOs; most muxable via GPIO matrix (GPIO46 input-only)
Wi-FiIEEE 802.11b/g/n (2.4 GHz), 20/40 MHz channels, 1T1R, up to 150 Mb/s; antenna diversity; 802.11mc FTMUSBFull-speed USB 2.0 OTG (integrated PHY), SRP/HNP, dynamic FIFO, configurable endpoints
MAC modesSimultaneous Station / SoftAP / Promiscuous; 4 virtual interfaces; WMM; A-MPDU/A-MSDU; Immediate Block ACKSPI4 controllers total (SPI0/1 for memory, SPI2/3 GP-SPI), up to 80 MHz STR; DDR support; DMA; up to 8-line modes
On-chip memory320 KB SRAM + 128 KB ROM; RTC FAST/SLOW 8 KB each; 4 Kbit eFuse (≈1792 bits user)I2S / AudioI2S master/slave, full/half-duplex, 8/16/24/32-bit, BCK up to 40 MHz; PCM supported; also used for parallel LCD/camera
External memorySPI/QSPI/OSPI/OPI flash & RAM, up to 1 GB addressable; cache-accelerated XIP; flash ICP supportI2CTwo controllers; Standard (100 kb/s) to ≤5 MHz (pull-up dependent); 7/10-bit addressing; dual-address mode
Integrated optionsVariants with embedded Flash (2 MB, 4 MB) and/or embedded PSRAM (2 MB): ESP32-S2FH2/FH4/FN4R2/R2UARTTwo UARTs up to 5 Mb/s, RS-232/RS-485/IrDA, HW CTS/RTS, DMA

Product Overview

A closer look at ESP32-S2 as a socs: functional summary, usage notes, and the features that matter in real designs.

  • USB device/host ready: Full-speed USB OTG with on-chip PHY streamlines accessories and field update paths.
  • ULP always-on sensing: A dedicated ULP coprocessor handles RTC GPIO/ADC/touch while the main CPU sleeps.
  • Hardened security chain: Secure boot + flash encryption + hardware AES/SHA/RSA and true RNG.

ESPRESSIF ESP32-S2 2.4 GHz Wi-Fi MCU — Overview & Specs

ESPRESSIF ESP32-S2 is a highly integrated, single-core 32-bit Wi-Fi microcontroller SoC built around an Xtensa® LX7 CPU running up to 240 MHz. It combines robust 2.4 GHz IEEE 802.11b/g/n wireless, extensive on-chip peripherals, and advanced security into a compact QFN-56 package—ideal for connected products that must balance performance, power, and cost.

The core platform provides 320 KB SRAM and 128 KB ROM, plus support for external SPI/QSPI/OSPI flash and RAM; certain device options integrate flash and/or PSRAM on-chip. This gives designers flexible memory footprints while maintaining fast code execution via cache acceleration.

For power-sensitive designs, ESP32-S2 delivers ultra-low-power operation through fine-grained clock gating, dynamic voltage and frequency scaling, and a capable ULP (ultra-low-power) coprocessor that can keep sensors, RTC, and GPIO wake sources alive during sleep. Multiple sleep modes—including light-sleep, deep-sleep, and hibernation—help products achieve long battery life without sacrificing responsiveness.

On the I/O side, the SoC exposes 43 programmable GPIOs and a generous peripheral set: SPI (up to four controllers), I2S, I2C, UART, RMT (IR), LED PWM (8 channels), pulse counters, a full-speed USB 2.0 OTG interface with integrated PHY, parallel and serial LCD interfaces, an 8/16-bit DVP camera interface, dual 12-bit SAR ADCs (up to 20 channels), dual 8-bit DACs, 14 capacitive touch channels, and an on-chip temperature sensor.

Security is first-class: secure boot (RSA-PSS), flash encryption (AES-XTS), integrated cryptographic accelerators (AES-128/192/256, SHA-2, RSA), true RNG, HMAC, and a Digital Signature peripheral—features that underpin device identity, firmware integrity, and data confidentiality from factory to field.

The built-in Wi-Fi subsystem supports single-stream 802.11n (20/40 MHz) with data rates up to 150 Mb/s, antenna diversity, and a complete MAC with multiple virtual interfaces for concurrent Station/SoftAP/Promiscuous operation—perfect for provisioning, diagnostics, and peer-to-peer use cases.

Finally, you benefit from a mature SDK (ESP-IDF), cloud connectivity examples, and commonly used “product features” out-of-the-box, which shorten time-to-market for consumer, industrial, and commercial IoT products.

Specifications

Parameter Value
CPU Xtensa® single-core 32-bit LX7, up to 240 MHz; 7-stage pipeline, 32 interrupts (6 levels)
Wi-Fi IEEE 802.11b/g/n (2.4 GHz), 20/40 MHz channels, 1T1R, up to 150 Mb/s; antenna diversity; 802.11mc FTM
MAC modes Simultaneous Station / SoftAP / Promiscuous; 4 virtual interfaces; WMM; A-MPDU/A-MSDU; Immediate Block ACK
On-chip memory 320 KB SRAM + 128 KB ROM; RTC FAST/SLOW 8 KB each; 4 Kbit eFuse (≈1792 bits user)
External memory SPI/QSPI/OSPI/OPI flash & RAM, up to 1 GB addressable; cache-accelerated XIP; flash ICP support
Integrated options Variants with embedded Flash (2 MB, 4 MB) and/or embedded PSRAM (2 MB): ESP32-S2FH2/FH4/FN4R2/R2
GPIO 43 programmable GPIOs; most muxable via GPIO matrix (GPIO46 input-only)
USB Full-speed USB 2.0 OTG (integrated PHY), SRP/HNP, dynamic FIFO, configurable endpoints
SPI 4 controllers total (SPI0/1 for memory, SPI2/3 GP-SPI), up to 80 MHz STR; DDR support; DMA; up to 8-line modes
I2S / Audio I2S master/slave, full/half-duplex, 8/16/24/32-bit, BCK up to 40 MHz; PCM supported; also used for parallel LCD/camera
I2C Two controllers; Standard (100 kb/s) to ≤5 MHz (pull-up dependent); 7/10-bit addressing; dual-address mode
UART Two UARTs up to 5 Mb/s, RS-232/RS-485/IrDA, HW CTS/RTS, DMA
LCD 8-bit serial RGB/8080/6800 via SPI2; 8/16/24-bit parallel via I2S; DE/VSYNC/HSYNC signals supported
Camera 8/16-bit DVP sensor interface up to 40 MHz (via I2S hardware)
PWM / RMT / Counters 8-ch LED PWM (18-bit duty at 1 ms), 4-ch infrared RMT Tx/Rx, 4× pulse counters
ADC Dual 12-bit SAR ADCs, up to 20 channels (analog-enabled pins)
DAC Two 8-bit DAC channels (independent)
Capacitive touch 14 capacitive-sensing channels (TOUCH1–TOUCH14)
Temperature sensor On-chip, –20 °C to 110 °C sensing range (chip internal)
Timers & watchdogs 4× 64-bit GP timers; 3 watchdogs (2× MWDT + 1× RWDT, multi-stage)
TWAI® (CAN 2.0) ISO 11898-1-compatible controller; 1 kb/s–1 Mb/s; listen-only/self-test; filters/FIFO/errors
Crypto AES-128/192/256, SHA-2 (FIPS 180-4), RSA (up to 4096-bit), RNG, HMAC, Digital Signature
Secure features Secure Boot (RSA-PSS), Flash Encryption (AES-XTS), key storage in eFuse, DS/HMAC identity
Power/voltage 2.8–3.6 V supply domains; VDD_SPI 1.8 V (LDO) or 3.3 V path per design
Low-power modes Modem-sleep / Light-sleep / Deep-sleep / Hibernation; ULP-FSM & ULP-RISC-V co-processors for always-on tasks
Typical currents Light-sleep ≈ 750 µA; Deep-sleep with ULP-FSM ≈ 170 µA, RTC timer only ≈ 20 µA (typ.)
RF TX power (typ.) 19.5 dBm @ 11b; 18 dBm @ 6 Mb/s (11g); up to 17/16.5 dBm @ MCS7 (HT20/HT40)
RX sensitivity (typ.) Down to –97 dBm (11b 1 Mb/s); –92 dBm (HT20 MCS0)
Frequency band 2.412–2.484 GHz (channels 1–14 region dependent)
Package QFN-56 (7 × 7 mm), variants differ in EPAD size (FN4R2 package note)
Operating temp. –40 °C to +105 °C (device-dependent; see series comparison)

Why designers choose ESP32-S2

Fast single-core compute with plenty of headroom. The LX7 at 240 MHz handles UI, protocol stacks, sensor fusion, and DSP-adjacent tasks (via I2S/PCM) while leaving margin for application code. With cache-accelerated XIP and flexible memory mapping, you can scale firmware and assets without sacrificing responsiveness.

Peripheral richness that reduces BOMs. USB OTG eliminates external bridges; the parallel LCD and DVP camera cut display/camera glue logic; 20-channel ADC + 2× DAC + 14 touch pads enable human-machine interfaces and sensing directly on the MCU. TWAI® brings straightforward CAN 2.0 connectivity to industrial devices.

Security built in from day one. Using secure boot and flash encryption anchored in eFuse, you can enforce signed images and at-rest confidentiality. Hardware AES/SHA/RSA accelerators, true RNG, HMAC, and the Digital Signature peripheral give you the tools for secure provisioning, attestation, and TLS performance.

Battery-friendly operations. Light-sleep and deep-sleep currents are optimized, and the ULP can periodically read sensors or touch pads and wake the main core on thresholds—ideal for wearables, e-paper displays, and remote sensors.

ESP32 S2 Applications

ESP32-S2 targets both consumer and industrial IoT scenarios. Typical use cases include:

  • Smart home & building: Wi-Fi smart plugs, switches and dimmers with smooth LED dimming; door locks with secure provisioning; lighting panels or thermostats with touch/LCD UIs; energy monitors using multi-channel ADC inputs.

  • Human-machine interfaces: USB gadgets, custom keyboards, touch sliders/wheels, and capacitive-touch appliances—combining touch sensing, PWM-driven feedback, and Wi-Fi connectivity.

  • Multimedia endpoints: OTT streaming accessories, internet radios, Wi-Fi speakers, and headsets that leverage I2S audio paths and Wi-Fi connectivity.

  • Cameras & vision: Compact Wi-Fi cameras or capture devices using the 8/16-bit DVP interface and USB for mass-storage or UVC-style modes (device architecture dependent).

  • Industrial & commercial: Wireless sensors, data loggers, and CAN-connected nodes (TWAI®) for factory floors; smart agriculture nodes (greenhouses/irrigation) using low-power sensing and periodic cloud sync.

  • Wearables & health: Smart bracelets/watches and monitors that benefit from low-power operation, touch, and secure updates over Wi-Fi.

  • Retail & POS: Connected kiosks, POS terminals with LCDs and barcode cameras, and service robots needing reliable Wi-Fi and USB.

  • Toys & education: Programmable Wi-Fi toys, remote control devices, proximity-sensing educational kits.

Variant guidance

The ESP32-S2 family spans flash/PSRAM options and temperature capabilities:

  • ESP32-S2: baseline device without embedded flash/PSRAM; –40 °C to +105 °C ambient.

  • ESP32-S2FH2 / FH4: devices with 2 MB or 4 MB embedded flash; –40 °C to +105 °C ambient.

  • ESP32-S2R2: embedded 2 MB PSRAM; –40 °C to +85 °C ambient.

  • ESP32-S2FN4R2: embedded 4 MB flash + 2 MB PSRAM; –40 °C to +85 °C ambient.

Use high-temperature “H” flash options for extended ambient ranges (e.g., appliances, light fixtures) and the embedded-PSRAM variants when your UI or buffering needs are higher.

Design notes

  • Clocking: the CPU requires an external 40 MHz crystal; audio PLL and internal oscillators service subsystems.

  • Power domains: multiple 3.3 V domains plus configurable VDD_SPI (1.8 V via internal LDO or 3.3 V rail). This allows powering down VDD_SPI in deep-sleep to reduce leakage.

  • Pin mux: most signals are freely routable via the GPIO matrix—great for PCB flexibility. Note GPIO46 is input-only.

  • Radio: typical TX powers meet spectral mask/EVM limits; receiver sensitivities support long-range low-rate as well as higher-throughput modes.

Design Resources

6 guides related to ESP32-S2 and socs topics — background reading before you freeze the schematic.

Frequently Asked Questions

FAQ for this socs (ESP32-S2). Focused on purchasing and design-check questions, not full datasheet reprints.

What is ESP32-S2?

USB device/host ready: Full-speed USB OTG with on-chip PHY streamlines accessories and field update paths. ULP always-on sensing: A dedicated ULP coprocessor handles RTC GPIO/ADC/touch while the main CPU sleeps. Hardened security chain: Secure boot + flash encryption + hardware AES/SHA/RSA and true RNG.

What type of component is ESP32-S2?

ESP32-S2 is a SoCs from ESPRESSIF.

What are the key specifications of ESP32-S2?

CPU: Xtensa® single-core 32-bit LX7, up to 240 MHz; 7-stage pipeline, 32 interrupts (6 levels); Wi-Fi: IEEE 802.11b/g/n (2.4 GHz), 20/40 MHz channels, 1T1R, up to 150 Mb/s; antenna diversity; 802.11mc FTM; MAC modes: Simultaneous Station / SoftAP / Promiscuous; 4 virtual interfaces; WMM; A-MPDU/A-MSDU; Immediate Block ACK; On-chip memory: 320 KB SRAM + 128 KB ROM; RTC FAST/SLOW 8 KB each; 4 Kbit eFuse (≈1792 bits user); External memory: SPI/QSPI/OSPI/OPI flash & RAM, up to 1 GB addressable; cache-accelerated XIP; flash ICP support.

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